1. Field
The following description relates to the allocation of address space to multi-port cache banks for reducing the concentration of data access at a particular cache bank.
2. Description of the Related Art
Generally, an off-chip memory has an operating speed that is slower than that of very-large-scale integration (VLSI) logic, and consequently system performance of the off-chip memory may be less efficient. To overcome the system performance of the off-chip memory, a chip may include a compact and high-speed memory. In this example, access to an off-chip memory may be avoided as much as possible, data process may generally be performed using an internal memory, and the off-chip memory may be used only when necessary. A typical example of an internal memory is a cache.
A recent increase in the integration of a VLSI system has lead to more devices accessing a single memory through multiple ports. A high-performance processor which includes multiple execution units typically includes multiple load/store units that simultaneously access a memory. In addition, a system that uses a multiple processor or a system on chip (SoC) in which a plurality of IPs are integrated into a single chip also has multiple processors and IPs that simultaneously access a memory.
To process simultaneous accesses from multiple IPs or ports, a memory with multiple ports is used. The multi-port cache includes two or more ports that can access a cache for reading and/or writing data, and is capable of processing simultaneous cache memory accesses through the multiple ports. In using multiple caches as described above, concentration of data access to a particular cache may occur thus decreasing the efficiency of the overall system performance.